Of Exams and inverters
(For those who are not familiar, the picture to the left is a CMOS inverter and is equivalent to a NOT gate. Basically, it inverts the input signal.)
Nus exams are like CMOS inverters. Go in with high confidence, but during the operation discharged all my charges and pull my confidence signal down to ground. So end result is a low confidence level for the output.
Perhaps next time should try to go in with low confidence. Then I will be charged up and subsequently can pull my confidence signal up to Vdd. Then got high output. Perhaps my switching speed from low to high wasn't fast enough. Maybe i should have increased my width (W) and reduced my length (L), since t(PLH) is inversely proportional to (W/L). Ok I am losing it...


One interesting and useful extension I discovered is 






