Of fyp and sigma delta modulator

Now that I am in my final year, one of the hot topics is none other than the final year project. Some of the conversations during gatherings, be it with ex-classmates, platoon mates or current school mates, have been centered around the opening of asking what each other’s FYP is about. More often than not, the responses from the other party usually make not much sense to me, unless of course the person is doing something general or something related to my area of specialization. Similarly, when I tell people I am doing a design of sigma delta modulator for my FYP, they go like wth is that?

So, I shall now present a brief overview of what sigma delta modulator is all about, as laymen as I can get. That is of course if you are even slightly interested in what I am doing, if not then just treat the rest of this entry as just some gibberish.

Now, in the world of electronics, there are 2 kinds of signals in general. They are either analog or digital. The signals from the outside world, sound for example, are analog in nature. These are the signals humans can understand. Yet, the computer or other microprocessor cannot. In order to process the analog data from the outside world, an interface is needed to bridge the 2 signals of different nature together. This is done using the Analog to Digital Converter (ADC).

How the ADC works is really, to put it very simply, approximating the analog data to a corresponding discrete level determined by the resolution. Due to this approximation, there will be some errors as the final digital output does not equal to the analog equivalent exactly. This error, or quantization noise, is inevitable but can be minimized. A sigma delta modulator is one such architecture of ADC to attempt to reduce this noise as much as possible.

The basic idea of a sigma delta modulator is to use the techniques of oversampling as well as noise shaping.

Oversampling is sampling at a frequency more than the nyquist rate, thereby reducing the amplitude of the quantization noise spectral density and spreading it over a wider range of frequency band while the total noise power is unaffected. Thus, by applying appropriate filters, the quantization noise out of the band of interest can be reduced.

Noise shaping further enhances the performance by means of filtering the quantization noise in the band of interest. This can be done by making a distinction between the noise and the input signal by means of a feedback loop filtering technique. Hence, by designing appropriate filters, the quantization noise inside the band of interest can also be reduced.

Improving the quantization noise is in essence improving the resolution of the ADC, and this is the objective of my project.

My FYP will start off with system level design using MATLAB, to design and determine the filter transfer function, order and coefficient and stuff, and also the oversampling ratio. After optimizing at the system level, I will then have to move into schematic level using the cadence ic design tools, where the modulator will be realized in transistors' level circuits. The technology that i will be using is 0.18um CMOS process technology. And if time allows, the layout design of the circuit will be implemented as well.

Now thats what i will be doing for the next 2 semesters.

A peek into EE4410

I was mentioning about my group wanting to chiong the project, and target to finish it by mid term. Well we are not joking. 2 weeks have gone by and we have already designed and completed the schematic for most of the parts. We are now trying to optimize our designs as well as think ahead for the layout design issues, such as area, mismatching and stuff. Hopefully the layout design will not posed too much problems. Oh wait, there's still a digital logic we have not complete yet. At first wanted to use verilog to design that part (which will be very simple), but the prof told us to use the digital library to implement it. That means using logic gates to do, think EE2006. And there isn't even a counter in the library for us to use! =(( Pure gates and mux. Sweet...




By the way, one of the sub-systems i am working on is the comparator. The comparator, as taken granted to be a block for most people that compares the 2 input and gives an indication of which is bigger at the output, requires some knowledge of the workings of the MOS transistor as an amplifier. I am actually quite impressed when i read and learn about how people implement the comparator, by making use of the characteristics of the op amp.

This is what goes on inside the black box, with current consumption of only 100nA!



And layout is more messy, here is just a testing layout for me to practice on cos i haven't take EE4415 which deals with abit on layout design, which proves to be really useful as my teammates all like very pro in layout except me.. =((

This is going to be a chiong sem...

Just attended the first lesson of this semester, which is EE4410 where the prof gave us a brief intro to the project that we are going to embark on. ECG signal acquisition system, which is to be designed and fabricated on a chip. Each project group consists of 4 people and each one is to design a subsystem of the chip, very much like EE2001, and then later integrate them together.




My part is going to be the ADC, which is quite challenging I would say. The architecture of this ADC is to be using the successive approximation algorithm, while my FYP is on another kind of architecture called the sigma delta modulation, which makes use of oversampling and noise shaping technique. From what I see now, both designs are quite hard one. Moreover, the dateline for the submission of the EE4410 final design is in week 9. This means the schematic design as well as the layout design to be ready for tape out. So, we have only around 2 months to complete this, which is really really rushed. I am so going to relive the days of EE2001 and eat, work, sleep on EE4410 everyday. Wait, there’s also my FYP hor? Wah, means eat, work, sleep on EE4410 and EE4001, like doing 2 FYPs.. Great, just great…

Now, some people went a bit crazy over the fact that my timetable in my previous entry was like so empty. Well, now to loosen them up a bit, here I posted another timetable which will very likely quite accurately reflects what I will be working on for the next month or so. It seems preposterous somewhat, but that’s really what my group intended to do. Complete the design by mid term and start worrying about our FYP.



Wish my good luck, will ya?

Of year 4 sem 1

Just received the email that I've successfully got my last module, EE4410 (Integrated circuits and system design)! The 8mc 2 semester-long project module....sheesh.. what have i got myself into?! Looks like need to reopen the NGDC for new applicants to support my grave digging activities.

EE4412 is rumored to be really really quite hard one..so much so that bk dun dare to take it....lol.. Eh then why i still take ah...gg

HR2002, bo bian have to take one, i wana graduate mah.

My FYP is going to be on IC design, topic is "Design of high resolution sigma-delta modulators" and my supervisor is the lecturer of EE4410, how convenient! Oh ya, ECE folks can check out your fyp allocation here.

So here goes, my timetable for the sem:



Sheesh..this must be the most disgusting timetable i've ever had.....(oops =p)

And ya, only 2 exams for this semester! (Both morning paper.. wtf)

Of how to confuse an idiot

Hilarious! Hahaa..

(Via)

Of cable skiing

Had my first try on cable skiing at SKI360 at east coast lagoon yesterday with Jevon and Zg. It was really really fun.

Before the skiing I was observing the ang mors doing it (sheesh there are really lots of them), they make it looks so simple lar. But, it’s not that easy for us.…

We took the 1 hour package, with student rates, so it's 27 bucks. I spent the first half hour swimming back to the shore more than I ski, always fell off at the first turn, trying to learn how to maneuver the board to go in the direction I want but ended up losing balance. Haha. The second half was where I finally got the technique and skied more than I swim! And yes, at least able to ski one round around the lagoon, unlike Jevon (oops). Poor little fellow, cannot keep balance on the board. Oh wait, it should be poor chubby one, too much fats at undesired position, causing imbalance in cg. You should have bend over more than anyone else. Ah, zg that ass, skiied before, so it was smooth-sailing for him.

You guys should try it if you haven't and I am probably going back for more! =)

How to make full use of your excess CORS bidding points

Note: This is intended for year 4 folks with lots of program or general points and dunno what to do with them.

General points.

This section is only for those with no more general modules to bid for and those points are just sitting down there collecting dust, damn there isn’t even any interest to accumulate.

Choose a target module of your choice, preferably those popular ones for best results. Dump in ALL your general points. See them scream in desperation when the highest bid shot up to 2k+.

Or just go bid for A FEW popular general modules; you will be potentially screwing up all their biddings when number of bidders exceeds the quota.

Drop the module just at the last moment just before the closed bidding ends.

Or heck, leave it as it is and get the module while denying one dude of his place and drop it later before the “W” period. Oh too bad you sore loser, who asked you to put only 1 point and never monitor the market ever since then.

Program points

Program points? For haven’s sake, just dump in everything to get your core and stop being such a calculative idiot. This is your last year, what were you expecting, NUS converting those excess points into cash for you at commencement?

Or if you really wana be an ass, go find a really hot module, with limited number of seats available, go dump in all your points. 5K+. They will crumble and cry for mother.

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I am really just kidding. Dun ever do that, you sick bastard.

Omg i am finally blogging....

Sheeesh... sorry for that absurd long period of absence. Oh my gosh, I didn’t blog for the whole of June and July? Has it really been that long? Time must have slip by so fast that I have lost track of it. You see, life as an intern has been really hectic and an assortment of after work activities further deny me of any possible opportunity to sit down and blog. There’s just so much to do, and even at times when I wanted to blog, there will be some dudes disturbing my rare moments of peace with repeated smses to play a game or 2 of DotA. No, actually I do welcome those games and enjoyed them at times, so much so that I played like almost every night for weeks. Yet, there are times where it got really tiresome and meaningless; what a boring game it has became. It’s ironic actually; I actually claimed that I will never get bored of this game because of the amazing replayability capacity with so many heroes to explore and so much different scenarios each time you play it.

Sorry I’ve digress. Ya, my internship is finally over. And as cliché as it may sound, it has been a really fulfilling 12 weeks of internship with DSI. The knowledge and experience gained will certainly be useful for me in the future, regardless of whether I continue in the embedded system industry. Even as an IC designer, there is knowledge gained with some digital design techniques I learnt from my fellow intern which could be really valuable. Quite genius that guy, created his own number theory that even the supervisor confused. Oh ya and did I mentioned that one of the intern in my group actually reads my blog and he was like introducing this blog to me, saying it provides really good information of modules for EE juniors like himself. Haha.

Ok I shall try to blog more from now, seeing that several people scolding me for being so lazy. What’s there to read here anyway? Such a boring blog.