I was mentioning about my group wanting to chiong the project, and target to finish it by mid term. Well we are not joking. 2 weeks have gone by and we have already designed and completed the schematic for most of the parts. We are now trying to optimize our designs as well as think ahead for the layout design issues, such as area, mismatching and stuff. Hopefully the layout design will not posed too much problems. Oh wait, there's still a digital logic we have not complete yet. At first wanted to use verilog to design that part (which will be very simple), but the prof told us to use the digital library to implement it. That means using logic gates to do, think EE2006. And there isn't even a counter in the library for us to use! =(( Pure gates and mux. Sweet...
By the way, one of the sub-systems i am working on is the comparator. The comparator, as taken granted to be a block for most people that compares the 2 input and gives an indication of which is bigger at the output, requires some knowledge of the workings of the MOS transistor as an amplifier. I am actually quite impressed when i read and learn about how people implement the comparator, by making use of the characteristics of the op amp.
This is what goes on inside the black box, with current consumption of only 100nA!
And layout is more messy, here is just a testing layout for me to practice on cos i haven't take EE4415 which deals with abit on layout design, which proves to be really useful as my teammates all like very pro in layout except me.. =((