Yay, completed the layout design of my comparator and it passed the DRC and LVS test as well as the post-layout simulation. Most of the rest of the parts are completed too, now what's left is to stitch up the different parts and do the final overall system simulation. And if it meets our specs, that basically concludes the module! Woot! (at least for this semester that is)
Then i can start doing my FYP, too long never touch liao.. haha.