Last friday was the official tape out date for EE4410. (Tape out in electronics terms is to submit the circuit design for fabrication.) So now that means we have nothing to do for this module till the next semester when the chip comes back, or at least close to nothing cos the foundry shoots back to us with some DRC(Design rules check) errors once in a while and we have to try to resolve those.Sucks, now i having problem with my FYP, dunno why the results weird weird one.
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