13/04: FYP CA3
17/04: FYP CA4
20/04: EE4415 Report deadline
27/04: EE4410 Report deadline
30/04: Last final exam paper in Nus, EE4415
Dying moments of my undergrad life. I think i am starting to miss my schooling days. No, not the exams or quizzes of course, everything else i guess. That also includes the things i did not do, having more fun and enjoying life while I can being one of them.
Yay, its that time of the year again where people goes into mugging mode, furiously printing out notes for the whole semester and searching for past years papers and what not. So after having slacked for the whole semester, let's check out what's installed for me this time.
Hmm, first paper's on the 20th of November, HR2002 (Human Capital in Organizations). Hey! That's during the reading week right? Damn.. Thought i am supposed to be still playing dota or something? Dang, there goes my plans.
Next paper is like, wow, 2 weeks later, 4th of December, EE4412 (Technology and modelling of silicon transistors). Ahh with that much amout of time in between, let's just take it easy lar.
And, that's it. Yup that's right! 2 papers nia. So slack, this must have been the most slack semester i ever had.
Its amazing how my results turns out exactly the same i predicted. So yup, it was as bad as i have expected, resulting in a slight drop in the cap. Well, its about time i guess, it has been rising steadily for the last few sems.. In summary, EE2001 saved me. Being the only A however, it had quite a difficult time trying to neutralize the negative effects of the rest of the modules, where the next best grade is B+. S/u option shall also be employed to help clear up the mess created by a B, although s/u-ing a B doesn't feel quite right, but well there's no other modules i can s/u and it does help me abit, so why not?
Next, the dateline for FYP selection will close next friday (6th June). Looking through the 700+ project proposals can be a pain in the ass and the search algorithm also just cannot make it. Spent some time last week during work to scan through the list and found that alot of them damn scary one, of course there are interesting ones like implementing a PS3 game/wii, some are just weird like laser for a king?? and also cute engineering, part of a series of research into the use of cuteness in engineering new interactive systems.
Here's the top 3 hottest projects as of now:
First 2 damn scary, so many people choose. Bet they never look at this stats, especially those choosing as 2nd and 3rd, sure no chance and wasting their choice slot one leh.
I finally submitted my project for EE3208...took the whole reading week plus last week to rush it out.
Here's some photos of the final product:
Ah i know success is missing a 'c', but i only limited to 6 characters mah...heh
I always thought software was hard. But i was so wrong as this project has proven to be that software is the easier part as compared to hardware. Why? Cos hardware is sometimes so hard to debug, there can be so many possibilities and uncertainties.
Ah, whatever, i still have 2 more papers to go.. and most people have already finished their exams liaoz. Sian..back to mugging.
Exams coming up again:
29/04/08 5pm @ MPSH1B: EG2401 Engineering Professionalism (Seat 557)
08/05/08 5pm @ MPSH1A: EE3304 Digital Control System (Seat 74)
10/05/08 9am @ ENG AUD: EE3407 Analog Electronics (Seat 28)
Time to start preparing for exams liao.
Spent the whole reading week doing EE3208's talking cash register. In the end, only the cash register part is done, the talking part is still having lots of problems. Seems like i am so going to get a shitty grade for this. Lucky still have s/u. Damn, wasted so much effort and time. in the end still have to s/u, so not worth it. Pissed with myself. =((
00:00 28 December 2007 to 23:59 on 30 December 2007
Important date and link you dun wana miss if you are going to declare your s/u option! So here it is.
And also if you are changing your TE to UEM, change it today via the Online Degree Requirement Check.
Well lets see, i am rather amused by my results, considering the fact that i am quite honestly thinking that i am screwed this semester. So it turns out i did pretty gd, although i would say that the general overall results wasn't really of that much interest to me than that one module which quite luckily i got a darn good grade which will at least allow me to even think of getting that 8mcs ic design module which i wana take in year 4.
It seems that pessimism sometimes do have its advantages. I was so certain that i am going to screw up big time for my dsp that i went to change the module from a technical elective into a UEM, so as to allow me to have the option of s/u-ing it. In the end, it turns out alright.
Our project module, we walked out of the presentation feeling screwed. No words can described how much we do not want to see a B-ish grade for a module we pump in so much effort and time on. But it turns out to be a B+, still B-ish but at least for me its decent enough.
Electronic gaming was a disaster. But still, i was expecting something much much worse. But at the end of the day, it doesn't matter cos this is going into the s/u dump for certain.
Microprocessor has been one of those very uncertain module i had. The paper itself brought about much uncertainty with all the uncertain answers i gave and those stupid mistakes i committed, and not forgetting to mention the uncertain project results which was never released, leaving us with no feedback as to how well we did whatsoever.
Integrated analog design. Well lets see, i enjoyed the module, learning the design methodology and the different topologies for circuit design. I spent darn lots of time on the project in order to get the most optimized results i possible could (optimization cost about 20% of the project grade). Although mine wasn't the best around, i do enjoy the learning process that led me to it, compromising certain specifications for another. The final paper went quite well and at the end of the day, i gave myself a pat on the back for a module well done.
This is actually my best sem...somehow..., after s/u-ing the gaming of course...
I believe fellow ECE folks could be interested in this. TE to UEM conversion (TUC) can now be done via the DRC (Degree Requirement Check) chip - DRC7417, which can be obtained here through our suppliers, nus. This particular chip is rather user-friendly and fast, with just mere clicks of a few buttons, your module can now be converted from a TE to a UEM. This is so to allow you to S/U that module if necessary after the results is being released.
This chip is only operational from now till 2nd December as well as on the 27th of December. Other than these dates, the DRC chip will not function!!
Modules converted to UEM using this chip can still be converted back to TE using the same chip if and only if the s/u option is not exercised on it. So if you convert to UEM and got a good result, later can change back to TE one. It says so here. Sue them if cannot convert back.
So there, you have been reminded. Check your NUS emails for more details.
Exams coming up:
26/11/07 1pm @ E5-03-20/21: EE3101 Digital Signal Processing (Seat 72)
28/11/07 5pm @ MPSH6: EE2007 Microprocessor System (Seat 179)
03/12/07 9am @ MPSH4: EE3408 Integrated Analog design (Seat 64)
07/12/07 9am @ MPSH6: EE3702 Electronic Gaming (Seat 67)
I need lots of luck this time. Haiz...
I was right when i said the worse module this sem is actually a GEM. Its quite bad, a B-, and i was wondering if its dumb to appeal for a module with mcq exams, cos the answers scripts are marked by machines mah. Then again, i kinda deserve the grade for not putting enough effort for this.
EE2009 and EE2012 came to me as a pleasant surprise.
C C Ko was serious when he say this in the last lecture: "Dun worry lar, if you can get 70 marks for the final and get at least 6/10 for ur e-test and go for all the labs, you get A+ already wat." And no i didn't get A+, but from the way i thought i am screwed, my grade is rather surprising - actually its pretty darn good.
As for EE2012, i honestly didn't know what i was doing half the time in the exams. The results showed either otherwise or that most of the ppl were just as blur as i was..
EE2010 is a disappointment, I think that arh they mixed up this one with my EE2009. Then again, as mentioned before, the module is rather competitive anyway. Actually it wasn't that bad lar, just that cos i expect too much from this one i guess..
I got what i hoped and expected for EE2006.
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I realised i am screwing myself up with wrong choices of non-cores modules these 2 years. My worse modules were all from non-cores: SC1101E (B-), EC1301 (C+) and GEK1527 (B-). 2 of those were a wrong choice right from the beginning as i was at a disadvantage with those with A level background in those field. But I did learn something useful out those modules and i thought that is what matters most. If only if i had better make use of my s/u points, then i wouldn't be feeling the pinch of what it would be like if those weren't graded.
This led me to think of actually doing EE modules for my UEM. I know it sounds crazy, but I have given it some thoughts. A while back, i was deciding between EE3406 (Microelectronics Materials) and EE3408 (Integrated Analog Design) cos the specialization rules is such that i can only choose one of these to fulfill my technical electives as they are under the same concentration. I will have to do EE3406 to qualify for the wafer fabrication sponsorship while EE3408 is my interest. So i believe the best solution is to take the latter as UEM.
And also, I might not be specializing in IC design but rather IC fabrication as i figured i would most probably not be able to get the most important module in that specialization, a 8MCs module on IC and system design, as it has a quota of 15 (i think) and its going to be merit based and resevered for folks with IC design sponsorship. I did applied for the IC design sponsorship but they didn't want me. So the next option for me is to go for IC fabrication and do a bit (2 actually) of design modules and see how it goes.
So, the modules i will be taking for the next 2 yrs will be as follows. Oh in case non-ECE ppl thinks why I so crazy go plan it out, our department requires us to plan out our technical electives modules for the next 4 sems and submit it through the module planner:
Yr 3 Sem1
EE3001 Technology assessment
EG2401 Engineering professionalism
EE2007 Microprocessor Systems
EE3406 Microelectronic Materials
EE3407 Analog Electronics
Yr 3 Sem2
EE2001 Analog & digital system design
IE2130 Quality Engineering
EE3304 Digital Control System
EE3408 Integrated Analog Design
Yr 4 Sem1
EE4001 B.Eng Dissertation
HR2002 Understanding human relations
EE4411 Silicon Processing Technology
EE4412 Technology & Modelling of Silicon Transistors
Yr 4 Sem2
EE4001 B.Eng Dissertation
EE4408 Silicon Device Reliability
EE4415 Integrated Digital Design
Oh yeah, exams are finally over and have been going out/playing games for the past 2 days, so no updates. For now, i am just going to do my usual AAR for the last 3 papers for the exams..
EE2006: Funny how I am quite devoid of any feelings after this paper. Dun feel any happiness nor any worries nor fear, nothing. I wonder why. The paper was quite a test of speed and i just had enough time to finish the paper, phew. It was probably due to the VHDL questions which requires writing ALOT of codes, i was so tempted to write "Please COPY and PASTE these for the next 15 lines lar!!" for 16 lines of similar codes.
EE2012: Contrary to the popular beliefs that the lecturer will once again reuse past year questions, this time he changed it somewhat, well.. both a good and bad thing at the same time, good in the sense that the time i spent learning the concepts are not wasted and bad in that i was quite stunned by some of the questions.
GEK1527: 100 MCQs. Do until headache, lots of guesses. Quite screwed i guess. Oh man, I cant believe the hardest module this sem is actually a gem.. =(
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Oh ya, added a few links to "Other Blogs" section in the sidebar, do check them out. Mostly taken from Ping.sg.
Also, the hits for this blog is going to hit 100,000 soon. Oh my gosh!
Now that the next paper is 3 days later, I can finally slack a bit (maybe 2 bits) and have a brief AAR on the last 2 papers.
EE2010. Well, as mentioned, the concepts for this module is pretty simple, so other than the 7 marks dead time question which I have absolutely no idea how to approach, the rest I believe are correct, conceptually. However, I am very prone to stupid careless mistakes, so…
EE2009.
“Flip. 1st question Fourier series, skip!! 2nd what what what? Why got bits one, thought this is signals? Panic. Turn back to the 1st. Damn! I really dun wana start learning Fourier series now leh… Turn to 2nd question again. Hmmm, nvm let’s go see 3rd question first. Convolution! Phew…”
The paper had 2 sections, 3 choose 2 from each section. The thing about such format is that whenever you can’t do the first question, you will feel very pressurized cos you will have to be able to do the other 2. And when you realized you can’t do the 2nd one as well, you know you are screwed. Then panic. When you panic, all is lost, unless you can get back your composure after the panic attack.
Fortunately, I managed to calm myself down and finished up question 3 then skip to section B first. I was more confident of digital signals (section B’s), and chose my questions comfortably. But, the irony is that, at the end of the day, I think that my section A (managed to solve question 2 and realized it’s not as hard as I thought, just because I din READ carefully the first time round) will be better. Why? Cos I screwed up the one question that I was supposedly most confident in – sampling theory.
Now, let’s see the trend. EE2004: never panic, good result. EE2005: never panic, good result. EE2011: panic, screwed result. Ok, I am screwed for EE2009.
When studying for exams, there will be a point where your brain voltage increases until the voltage drop across the oxide at the drain brain edge equals that of the terminal voltage. This is when your brain goes into saturation mode and whatever increase in input doesn't affect the output anymore.
This is detrimental to the exam preparation as it might result in the loss of the electrons to useless stuff like msn, tv, games and blogging.
But fear not! Your brain channel length is not always a constant as what the ideal brain current-voltage relationship have assumed. Thus, due to the effects of channel length modulation, your brain current still can increase a little bit even after saturation.
But the marginal gain from saturation of the brain is very very little, so its better to let the electrons wander off and let the brain voltage drops till the linear region. It's in the linear region that your brain voltage will increase linearly with your input and thus making your learning, studying, mugging more effective.
Dun mug too hard guys, take a break once in a while and blog crappy stuff like this! Ha. =)
24th Apr 9am: EE2010 System and controls
Concepts relatively simple, bell curve's going to be scary. *Shudder*
26th Apr 1pm: EE2009 Signals
Seemingly slack module with a light-hearted lecturer. Alot of self-learning needs to be done wor..
30th Apr 5pm: EE2006 Digital Design
An interesting and enriching module which inspired me to take on more design modules.
2nd May 9am: EE2012 Analytical Methods in ECE
Very very maths intensive, most people dread this module.
4th May 2.30pm: GEK1527 Genes and society
Basically i feel that i am quite screwed for this. The lecturer and the contents are great, just that i am spending way too little time on this.
Ah well, good luck everyone for the exams!
3 more weeks to vacation! Weeee!
Mission Results for Operation final exam is out:
EE2004 - Electronic devices
One of my more confident modules, efforts paid off. Best grade that I ever got in NUS.
EE2005 - Electronics
Very surprising considering that I left quite abit of blanks for the final exams. This is in fact my most confident module for the semester which turned out rather disappointing during the exam, and yet now a sigh of relief.
SSA2204 - Nation Building in Singapore
Escaped successfully!
EE2011 - Engineering Electromagnetics
Bloody hell. Agent Smith slowed me down in my pursuit. Rumor has it that we are going to deal with him again in the coming semester in mission EE2012: Analytical methods in ECE. Watch out Smith.
ST2334 - Probability and Statistics
Indeed underestimated the enemies, but still glad with the result.
GEM2900 - Understanding uncertainty and statistical thinking
Well, slightly lower than what I have expected, but still an okay grade nonetheless.
All in all, it was a good semester for me, not only with the results but I sort of found my field of interest and more or less confirm what I will be specializing in for my upper years. Cheers to that.
It appears that everyone was checking their exam results while Mitch, Jere and I were playing winning eleven and having supper at Geylang on Friday night... So when some people came asking me whether I saw my results, I was like "hello? I am pretty sure I have yet to celebrate Christmas, how to check results?" When I eventually came to know about the leakage (which happened in previous sems before, according to a friend), the webpage has already been removed. Looks like I have been missing out some excitement ensuing from this leakage of results, though some said that those were just the raw score before moderation. Heard some people did pretty well, some not good. Yet from what i gathered, I hope that's not the finalized results.
Ignorance is indeed a bliss.
One-liner debrief for operation final exam 2006 with reference to the mission briefing for operation final exam 2006:
Operation EE2004
The real battle was indeed much worse than the simulations.
Operation EE2005
Although Miller did not set up any ambush, a certain level shifter monster almost knocked me unconscious around 1 hr into the mission
Operation SSA2204
Smoke grenade and flash bangs was indeed of great help, but I too siao on, even threw in a few fragmentation grenade as well.
Operation EE2011
Agent Smith not only tried to confuse me, he actually shot me right in the face.
Operation ST2334
We shouldn’t have underestimated the enemies.
Operation GEM2900
Uncertainty of understanding uncertainty continues to prevail.
Nus exams are so good in making me feel dumb. In my rush to finish a question within the last 5 mins of my paper, I computed something so ridiculous that I think I should go kill myself. Who the hell makes this kind of careless mistake?? =(
To the optimist, "Phew, at least I finished half the paper sia!"
To the pessimist, "Wtf! I left half the freaking paper empty can? Die lar."
To the engineer, "The exam questions are twice as much as it needs to be."
(For those who are not familiar, the picture to the left is a CMOS inverter and is equivalent to a NOT gate. Basically, it inverts the input signal.)
Nus exams are like CMOS inverters. Go in with high confidence, but during the operation discharged all my charges and pull my confidence signal down to ground. So end result is a low confidence level for the output.
Perhaps next time should try to go in with low confidence. Then I will be charged up and subsequently can pull my confidence signal up to Vdd. Then got high output. Perhaps my switching speed from low to high wasn't fast enough. Maybe i should have increased my width (W) and reduced my length (L), since t(PLH) is inversely proportional to (W/L). Ok I am losing it...
