Spiderman spotted at NUS central library 23/04/09

Holy shit! Spidey in NUS! Lmao!

EE4410 Chip Micrograph

The following shows the chip micrograph of the chip we designed in the module EE4410.







Notice the last one got 4 pacman ghost? Haha, its our logo, representing the 4 mooty aliens of this project, the 3rd one is xiao chuan cos that one has got a horn! Moo!

The final leg

13/04: FYP CA3
17/04: FYP CA4
20/04: EE4415 Report deadline
27/04: EE4410 Report deadline
30/04: Last final exam paper in Nus, EE4415


Dying moments of my undergrad life. I think i am starting to miss my schooling days. No, not the exams or quizzes of course, everything else i guess. That also includes the things i did not do, having more fun and enjoying life while I can being one of them.

Sigma Delta

This is the output for my fyp, sigma delta modulator. Generally, the noise shaping is working; notice how the low frequency components have lower noise compared to the higher frequency ones. This is because the low frequency noise has been "shifted" to the higher frequency part so that the signal of interest, which is in the lower frequency domain, is not affected by noise.

However, the result is far from expectation. 80dB of SNR is a far cry from the desired 120+dB that is required of a 20-bits sigma delta modulator. Sad. Sibeh sian. =((

And most people reading this dunno what i talking about. Also sibeh sian. No one can help me..

My first designed chip!

Yay, we just got back our chip, the one we spent one sem to design. So before sending for fabrication, our design was working pretty fine. Now that the real thing is fabricated, will it still work as we intended? That will be the task for us this semester, to perform all kinds of test on the chip to verify our design.









Initial test shows some system working fine. The ADC seems to be ok, but only 1 input tested. LNA seems to have lots of problems. Bandgap is ok. More tests will be perform for the next few weeks and if it works, yay! If not... then pray for at least a b+... lol

Exams is here again

Yay, its that time of the year again where people goes into mugging mode, furiously printing out notes for the whole semester and searching for past years papers and what not. So after having slacked for the whole semester, let's check out what's installed for me this time.

Hmm, first paper's on the 20th of November, HR2002 (Human Capital in Organizations). Hey! That's during the reading week right? Damn.. Thought i am supposed to be still playing dota or something? Dang, there goes my plans.

Next paper is like, wow, 2 weeks later, 4th of December, EE4412 (Technology and modelling of silicon transistors). Ahh with that much amout of time in between, let's just take it easy lar.

And, that's it. Yup that's right! 2 papers nia. So slack, this must have been the most slack semester i ever had.

1 module down!

Last friday was the official tape out date for EE4410. (Tape out in electronics terms is to submit the circuit design for fabrication.) So now that means we have nothing to do for this module till the next semester when the chip comes back, or at least close to nothing cos the foundry shoots back to us with some DRC(Design rules check) errors once in a while and we have to try to resolve those.

Sucks, now i having problem with my FYP, dunno why the results weird weird one.

Of layout design of comparator

Yay, completed the layout design of my comparator and it passed the DRC and LVS test as well as the post-layout simulation. Most of the rest of the parts are completed too, now what's left is to stitch up the different parts and do the final overall system simulation. And if it meets our specs, that basically concludes the module! Woot! (at least for this semester that is)

Then i can start doing my FYP, too long never touch liao.. haha.

The most expensive module

EE4410 (Integtated circuit and system design), it cost around $6k to fabricate the chip that we design. So its around $1.5k per person, since there are 4 person in one group. So that just makes this the most worth it module to take. Not too sure about the grade though. But then again, i think our group is doing quite well, at least we are almost done with integration at schematic level, now proceeding with layout design.

Of fyp and sigma delta modulator

Now that I am in my final year, one of the hot topics is none other than the final year project. Some of the conversations during gatherings, be it with ex-classmates, platoon mates or current school mates, have been centered around the opening of asking what each other’s FYP is about. More often than not, the responses from the other party usually make not much sense to me, unless of course the person is doing something general or something related to my area of specialization. Similarly, when I tell people I am doing a design of sigma delta modulator for my FYP, they go like wth is that?

So, I shall now present a brief overview of what sigma delta modulator is all about, as laymen as I can get. That is of course if you are even slightly interested in what I am doing, if not then just treat the rest of this entry as just some gibberish.

Now, in the world of electronics, there are 2 kinds of signals in general. They are either analog or digital. The signals from the outside world, sound for example, are analog in nature. These are the signals humans can understand. Yet, the computer or other microprocessor cannot. In order to process the analog data from the outside world, an interface is needed to bridge the 2 signals of different nature together. This is done using the Analog to Digital Converter (ADC).

How the ADC works is really, to put it very simply, approximating the analog data to a corresponding discrete level determined by the resolution. Due to this approximation, there will be some errors as the final digital output does not equal to the analog equivalent exactly. This error, or quantization noise, is inevitable but can be minimized. A sigma delta modulator is one such architecture of ADC to attempt to reduce this noise as much as possible.

The basic idea of a sigma delta modulator is to use the techniques of oversampling as well as noise shaping.

Oversampling is sampling at a frequency more than the nyquist rate, thereby reducing the amplitude of the quantization noise spectral density and spreading it over a wider range of frequency band while the total noise power is unaffected. Thus, by applying appropriate filters, the quantization noise out of the band of interest can be reduced.

Noise shaping further enhances the performance by means of filtering the quantization noise in the band of interest. This can be done by making a distinction between the noise and the input signal by means of a feedback loop filtering technique. Hence, by designing appropriate filters, the quantization noise inside the band of interest can also be reduced.

Improving the quantization noise is in essence improving the resolution of the ADC, and this is the objective of my project.

My FYP will start off with system level design using MATLAB, to design and determine the filter transfer function, order and coefficient and stuff, and also the oversampling ratio. After optimizing at the system level, I will then have to move into schematic level using the cadence ic design tools, where the modulator will be realized in transistors' level circuits. The technology that i will be using is 0.18um CMOS process technology. And if time allows, the layout design of the circuit will be implemented as well.

Now thats what i will be doing for the next 2 semesters.

A peek into EE4410

I was mentioning about my group wanting to chiong the project, and target to finish it by mid term. Well we are not joking. 2 weeks have gone by and we have already designed and completed the schematic for most of the parts. We are now trying to optimize our designs as well as think ahead for the layout design issues, such as area, mismatching and stuff. Hopefully the layout design will not posed too much problems. Oh wait, there's still a digital logic we have not complete yet. At first wanted to use verilog to design that part (which will be very simple), but the prof told us to use the digital library to implement it. That means using logic gates to do, think EE2006. And there isn't even a counter in the library for us to use! =(( Pure gates and mux. Sweet...




By the way, one of the sub-systems i am working on is the comparator. The comparator, as taken granted to be a block for most people that compares the 2 input and gives an indication of which is bigger at the output, requires some knowledge of the workings of the MOS transistor as an amplifier. I am actually quite impressed when i read and learn about how people implement the comparator, by making use of the characteristics of the op amp.

This is what goes on inside the black box, with current consumption of only 100nA!



And layout is more messy, here is just a testing layout for me to practice on cos i haven't take EE4415 which deals with abit on layout design, which proves to be really useful as my teammates all like very pro in layout except me.. =((

This is going to be a chiong sem...

Just attended the first lesson of this semester, which is EE4410 where the prof gave us a brief intro to the project that we are going to embark on. ECG signal acquisition system, which is to be designed and fabricated on a chip. Each project group consists of 4 people and each one is to design a subsystem of the chip, very much like EE2001, and then later integrate them together.




My part is going to be the ADC, which is quite challenging I would say. The architecture of this ADC is to be using the successive approximation algorithm, while my FYP is on another kind of architecture called the sigma delta modulation, which makes use of oversampling and noise shaping technique. From what I see now, both designs are quite hard one. Moreover, the dateline for the submission of the EE4410 final design is in week 9. This means the schematic design as well as the layout design to be ready for tape out. So, we have only around 2 months to complete this, which is really really rushed. I am so going to relive the days of EE2001 and eat, work, sleep on EE4410 everyday. Wait, there’s also my FYP hor? Wah, means eat, work, sleep on EE4410 and EE4001, like doing 2 FYPs.. Great, just great…

Now, some people went a bit crazy over the fact that my timetable in my previous entry was like so empty. Well, now to loosen them up a bit, here I posted another timetable which will very likely quite accurately reflects what I will be working on for the next month or so. It seems preposterous somewhat, but that’s really what my group intended to do. Complete the design by mid term and start worrying about our FYP.



Wish my good luck, will ya?

Of year 4 sem 1

Just received the email that I've successfully got my last module, EE4410 (Integrated circuits and system design)! The 8mc 2 semester-long project module....sheesh.. what have i got myself into?! Looks like need to reopen the NGDC for new applicants to support my grave digging activities.

EE4412 is rumored to be really really quite hard one..so much so that bk dun dare to take it....lol.. Eh then why i still take ah...gg

HR2002, bo bian have to take one, i wana graduate mah.

My FYP is going to be on IC design, topic is "Design of high resolution sigma-delta modulators" and my supervisor is the lecturer of EE4410, how convenient! Oh ya, ECE folks can check out your fyp allocation here.

So here goes, my timetable for the sem:



Sheesh..this must be the most disgusting timetable i've ever had.....(oops =p)

And ya, only 2 exams for this semester! (Both morning paper.. wtf)

How to make full use of your excess CORS bidding points

Note: This is intended for year 4 folks with lots of program or general points and dunno what to do with them.

General points.

This section is only for those with no more general modules to bid for and those points are just sitting down there collecting dust, damn there isn’t even any interest to accumulate.

Choose a target module of your choice, preferably those popular ones for best results. Dump in ALL your general points. See them scream in desperation when the highest bid shot up to 2k+.

Or just go bid for A FEW popular general modules; you will be potentially screwing up all their biddings when number of bidders exceeds the quota.

Drop the module just at the last moment just before the closed bidding ends.

Or heck, leave it as it is and get the module while denying one dude of his place and drop it later before the “W” period. Oh too bad you sore loser, who asked you to put only 1 point and never monitor the market ever since then.

Program points

Program points? For haven’s sake, just dump in everything to get your core and stop being such a calculative idiot. This is your last year, what were you expecting, NUS converting those excess points into cash for you at commencement?

Or if you really wana be an ass, go find a really hot module, with limited number of seats available, go dump in all your points. 5K+. They will crumble and cry for mother.

--------------------------

I am really just kidding. Dun ever do that, you sick bastard.

Of results and FYP selection

Its amazing how my results turns out exactly the same i predicted. So yup, it was as bad as i have expected, resulting in a slight drop in the cap. Well, its about time i guess, it has been rising steadily for the last few sems.. In summary, EE2001 saved me. Being the only A however, it had quite a difficult time trying to neutralize the negative effects of the rest of the modules, where the next best grade is B+. S/u option shall also be employed to help clear up the mess created by a B, although s/u-ing a B doesn't feel quite right, but well there's no other modules i can s/u and it does help me abit, so why not?

Next, the dateline for FYP selection will close next friday (6th June). Looking through the 700+ project proposals can be a pain in the ass and the search algorithm also just cannot make it. Spent some time last week during work to scan through the list and found that alot of them damn scary one, of course there are interesting ones like implementing a PS3 game/wii, some are just weird like laser for a king?? and also cute engineering, part of a series of research into the use of cuteness in engineering new interactive systems.

Here's the top 3 hottest projects as of now:



First 2 damn scary, so many people choose. Bet they never look at this stats, especially those choosing as 2nd and 3rd, sure no chance and wasting their choice slot one leh.

Of Chartered and more on internship

Yay, it's weekend again! The 2nd week of internship past by real fast. Cos monday is public holiday, tuesday i did half day cos got interview with Chartered, Friday also half day cos DSI got some dinner and dance thingy, so we were released early.

The interview with Chartered was quite horrible. It was largely due to the fact that i did not understand how Chartered fit in in terms of designing role. As Chartered is well known for being a fabrication foundry and only does manufacturing of wafer from the designs of their customers , i was being questioned as to how can i contribute as an ic designer. I mentioned a few things like verification, testing and stuff, but each answer was backfired as those weren't exactly what they are dealing with; obviously i didn't do my homework.

Technical question were alright, was asked to design an inverter using CMOS process, that one i did ok, with the circuit as well as the explanation. Then, the next one was how to simulate and measure the RC time constant. This one i blanked out, damn it's only after the interview i realized how easy it was. The remaining of the interview was the most jialat one, the interviewer kept reiterating: So you really wana be an ic designer? for like 10 times or Tell me why should we give you the scholarship and not the rest of your peers? Do you think Chartered is really the right choice for you? You sure you wun regret?


Ok back to my internship. I have been given more tasks after completing the first one. I also implemented what i have learnt in EE3208 (timer interrupt) into my project, in order to make my timing more accurate. Now thinking back, even though EE3208 might be my worse module this sem, i actually learn alot from the module and applied the most in my work here in DSI. This is the reason why you should take design module, you get to do hands on project and not just theory only. And of course you get to tell people you did something impressive in the module like:"Hey i did a talking cash register in my module.", rather than:"Erm, well, I learnt how to do fast fourier transform." (Erm, i have nothing against the signals and comms folks ah, this is just an example..lol)

Also, other than doing my microcontroller programming, I am also writing a simple game using visual C++ just for fun after I have finished my task. It's just a simple text based game where you get to fight monsters based on dungeons and dragons rule but a more simplified version to ease the complexity of my program..

Oh yeah, by the way, even though i am working in a research institute, I am doing pretty much industry work rather than research. I am part of the team that is going to produce something that is going to be sell for industry use. Which kinda answer my question on why everyone else is like studying... while i am doing actual work...

Alright, that's all for now.

Of EE3208 completed!!

I finally submitted my project for EE3208...took the whole reading week plus last week to rush it out.

Here's some photos of the final product:





Ah i know success is missing a 'c', but i only limited to 6 characters mah...heh


I always thought software was hard. But i was so wrong as this project has proven to be that software is the easier part as compared to hardware. Why? Cos hardware is sometimes so hard to debug, there can be so many possibilities and uncertainties.

Ah, whatever, i still have 2 more papers to go.. and most people have already finished their exams liaoz. Sian..back to mugging.

Exams again...

Exams coming up again:

29/04/08 5pm @ MPSH1B: EG2401 Engineering Professionalism (Seat 557)
08/05/08 5pm @ MPSH1A: EE3304 Digital Control System (Seat 74)
10/05/08 9am @ ENG AUD: EE3407 Analog Electronics (Seat 28)

Time to start preparing for exams liao.

Spent the whole reading week doing EE3208's talking cash register. In the end, only the cash register part is done, the talking part is still having lots of problems. Seems like i am so going to get a shitty grade for this. Lucky still have s/u. Damn, wasted so much effort and time. in the end still have to s/u, so not worth it. Pissed with myself. =((

The day my keypad and 7 segment LED started working!!

Finally finally!! After 2 days of debugging and stressing my ass off, my keypad and 7 segment finally work! Ahh this is for yet another project module, EE3208. Deadline for this project is 7th may wor...

Just moments ago, i finally found the error in my codes that made my 7 segment went berserk earlier in the lab. Here, my system display 543210 and then switch to 9876 after 1 second and 543210 again and so on. This is just a test program to test the 7 segment.






More photos, taken after i wire wrap. Yes wire wrap, bloody hell, you've gotta marvel at the wonderful invention of wire wrapping, making you connect wires for more than TEN TIMES longer than you otherwise would if using breadboard instead and poking wires into those lovely holes. Now, this damn stupid thing cause me like weeks to connect just a simple system...






Now, i better go try to make the sound part work, if not i am still quite screwed. There's a reason why the project is called "Talking cash register"..

EE2001 - The Airport of the Future!

Finally, after 1 semester of hard work, pulling of hair wires, soldering accidents extension of wires, late nights and stressing over whether we have enough features, the 6 MCs project module came to an end after a rather good presentation last Friday.

Our team had lots of fun in this project. Its always great to see our concepts and design materialize into the real working product. And we also put in alot of effort in making the model looks professional, and it all pays off because in the end it really looks very good and impressive, and the sense of achievement is just beyond words can describe. We also put in alot of effort on the GUI and SMS, learning much more things than required, to present our project in the best way possible.

In all, it was a great project and no matter what kind of grades we get, we can proudly say we did our very best!

Now, let the photos do the talking.



EE2001, The Airport of the Future, presented by group 4-03:



The Graphical User Interface (GUI):



The GUI has an overview of our entire airport and can control certain features as well as performing real time updating of the status of the transit rooms allocation as well as the smart car park. One of our best features in this project.


The smart transit rooms allocation system:



This one got a rotating platform plus a travellator on top. It basically allocate traveler to the nearest available transit room. Spent a great deal of time to make this feature as perfect as possible.

The smart car park:


The car park provides guiding light for drivers to the nearest available slot. It also have a room booking system and the driver will be directed to the slot nearer to the transit rooms.

The smart queuing system and the SMS system:




Smart queuing system requires traveler to login into the system by first obtaining a one time password from the SMS system and then entering into the keypad in the waiting area. The system then prompt travelers to board plane row by row based on their seat numbers and whether that passenger to the particular seat has login.

The greeting robot and interactive directory:




Next comes the greeting robot which turns to face the travelers as they come out of the car park. On it is the interactive directory where travelers can check out what shops are there in the shopping area as well as the route to take to get there. Moreover, they can have the map sms to their handphone!


The Lounge power management system:



Solar panel for the lounge:


Smart energy control allows the fan to blow at speed corresponding to the number of people in the lounge. Also lighting depends on the amount of sunlight on the solar panel.


More photos of us at work:





Red bull kept us awake all night through! (Eh actually only I drank...together with coffee and had a terrible stomachache the next day..jeez )



























Messy wiring below....




Planning stage for the model:


Taking measurements:



The designer at work:




More messy wirings during testing phase:




Once again, this is The Airport of the Future!





Of course, a great project should end with a celebration of sorts. Right after the presentation, we treated ourselves to a sumptuous meal at Sakura!





Okay no more photos after this, too busy eating..lol.


GG!